Phase 3 — PCB Layout

Development board PCB designed in KiCad with hand-solderable components. Schematic and component placement complete — ready for student review and routing.

Overview

This is a development board designed to characterise and test the PillStim stimulation circuit. It replicates the pill electronics with hand-solderable components, and adds a debug harness that greatly improves testing speed and data collection. The board is designed around three external connections — an STLINK-V3PWR, a Digilent Analog Discovery 3, and an external storage capacitor — which together provide everything needed to fully test the circuit.

Inputs

STLINK-V3PWR	14-pin header (J2) + power terminals to VSTLINK (J5) SWD debug, UART data, and regulated power supply to the board — all from a single instrument
Analog Discovery 3	30-pin IDE header (J8) 16 digital channels observe all MCU I/O. Waveform generator provides test signal injection (e.g. external boost clock). Two scope inputs are routed through front-panel selectors to any test point.
Storage capacitor	External header (J4) External capacitor allows easy swapping of values during characterisation without rework
Batteries	2× SR927 coin cells (BT1, BT2) or external source via JST (J3) Used in battery mode — not required during debug, where the STLINK provides power

Outputs

Electrodes	Biphasic current stimulation output The primary output of the PillStim circuit — drives the selected load (tissue model, LED, or capacitor)
AD3 scope channels	Two analog outputs routed via front-panel selectors (SW4, SW5) Any combination of test points can be observed without re-wiring. Electrode 1 and 2 are on separate selectors to allow differential measurement across the load.
AD3 digital channels	All MCU I/O visible on the AD3 logic analyser H-bridge timing, pump clock, DAC output, range select — captured in the same time base as the analog channels
UART	Serial data via STLINK-V3PWR Firmware telemetry, ADC readings, and diagnostics streamed to the host
LED indicators	D11, D12 Quick visual confirmation that anodic and cathodic phases are firing — available when load selector is set to LED

User Interface

Five rotary switches along the bottom edge configure the board for different test scenarios. No re-wiring required between tests.

Scope 1 (SW5)	ELEC1, AMP, CSI, BOOST, VSEN, NC Select which signal is routed to AD3 scope channel 1
Scope 2 (SW4)	ELEC2, AMPBUF, CSV, VHV, BOOST, NC Select which signal is routed to AD3 scope channel 2. Electrode 1 and 2 are on separate selectors to enable differential measurement across the tissue load.
Load (SW6)	Tissue — Randles cell model for realistic testing and shorting verification LED — quick visual debug to confirm anodic and cathodic phases are working Cap — capacitive load to observe current waveform
Power Source (SW7)	VHV_5V — bypass mode, powers H-bridge from AD3 +5V supply (bypasses boost) Default — debug mode, circuit fully powered by STLINK-V3PWR BAT — battery mode, powered by button cells or external source via J3
Test Signal (SW8)	Default — normal operation BST_DISC — boost circuit clocked by AD3 waveform generator ADC_TEST — ADC test mode
Reset (SW1)	MCU hardware reset Tactile pushbutton, active low

Board Details

Revision	V1 — 29 March 2026
EDA tool	KiCad — free, open source
Source files	hardware/kicad/ — GitHub repository
Status	Components placed, unrouted — ready for review and routing
Assembly	Hand-solderable — all packages accessible with iron

Next Steps

01

Access KiCad Files

Clone the repository. All KiCad project files are located in pillstim-project/hardware/kicad/. KiCad is free to download.
Required
02

Schematic Review

Open the schematic and check for obvious issues — missing connections, incorrect net names, power rail errors, or logic mistakes.
Required
03
Component Verification

Review each component to confirm:
- Correct part number (MPN) matches the BOM
- Pin-out matches the datasheet
- Footprint matches the selected package
Required
04

MCU Pin Assignment Review

Verify that every MCU pin has been assigned to a peripheral function it actually supports. Not all pins can do all things — check the STM32L052K8T6 datasheet alternate-function table and confirm that PWM outputs, DAC, ADC inputs, SWD, UART TX/RX, and GPIOs are all on pins that provide those specific functions.
Required
05

PCB Pin-Out Check

Cross-reference the PCB footprints against datasheets. Pay particular attention to through-hole components where orientation can be mixed up — connectors, switches, and the coin cell holders.
Required
06

Route the PCB

With the schematic verified, route all connections in KiCad. This is the main student exercise — tracing each net from schematic to copper builds understanding of the full circuit.
Required
07
LTSpice Simulation (Extension)

Simulate two critical sub-circuits with real component models:
- Diode boost circuit — Dickson charge pump with real diode and capacitor models, driving a 200 µF capacitive load. Verify charge-up time and output voltage.
- H-bridge with shorting circuit — supply with a current source and verify biphasic operation. Timing is critical: the electrode must be shorted before reversing current direction to avoid charge imbalance.
Extension

Review gate: Once the schematic and footprints are verified and the board is routed, submit the KiCad files for review before ordering. I will review the PCB prior to fabrication submission.

Ordering

Order Now

These can be ordered immediately while schematic review and routing are in progress.

STLINK-V3PWR	2× — debug, UART, and power supply for the board
Full BOM	2× — second set as spares for rework

Order After Routing

Once the board is reviewed, routed, and DRC-clean, generate fabrication files and order from JLCPCB. There is a JLCPCB plugin for KiCad that handles export directly. They are extremely fast.

PCB blanks	2× — bare boards for hand assembly
PCB assembled	2× — factory-assembled boards
Layers	2-layer recommended — 4-layer acceptable if routing requires it

Parallel work: Firmware development will proceed in parallel with PCB fabrication. The schematic and component selection are finalised, so the hardware interface is de-risked and firmware can target the real pin assignments.